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soltanloo/DirectMappedCache: A simple direct-mapped cache modeled by Verilog. Part of Spring 2019 Computer Architecture course at the University of Tehran. · GitHub

Name		Name	Last commit message	Last commit date
.gitignore		.gitignore
Cache.v		Cache.v
CacheDataMemory.v		CacheDataMemory.v
Controller.v		Controller.v
Datapath.v		Datapath.v
DirectMappedDataCache.v		DirectMappedDataCache.v
MainMemory.v		MainMemory.v
TB.v		TB.v
TagMemory.v		TagMemory.v
VMemory.v		VMemory.v

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A simple direct-mapped cache modeled by Verilog. Part of Spring 2019 Computer Architecture course at the University of Tehran.

cache direct-mapped-cache verilog

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