A low-latency LRU approximation cache in C++ using CLOCK second-chance algorithm. Multi level cache too. Up to 2.5 billion lookups per second.

2D terrain divided into tiles, compressed on CPU, decompressed on GPU, with caching to decrease PCIE bottleneck and VRAM requirement for very big terrains.

A simple direct-mapped cache modeled by Verilog. Part of Spring 2019 Computer Architecture course at the University of Tehran.

The repository simulates direct-mapped , four way set associative and 8 way set associative cache.

CPP Program to simulate a Generalized Cache behaviour

Dual hierarchy (L1 and L2) cache simulator with direct mapping and two way associative configurations. Project for Computer Organization class.

Simple Computer Architecture using direct mapped cache memory. Designed in VHDL and Quartus for DE0_CV FPGA.

A simple implementation of a Direct Mapped Cache and Set Associative Cache in C++. Supports for different sizes of the cache, block, #ways, etc.

Low-level programming assignments, "Low-Level Programming" (TDT4258) course, fall 2023.

A parameterized Verilog implementation of a Direct-Mapped Write-Back Write-Allocate Cache Controller with configurable memory latency.

cache controller verification

Modular direct-mapped cache controller in Verilog featuring, write-back and write-allocate policies, FSM-based control, dirty block eviction, and self-checking verification

My Solutions to Computer Architecture Course Practical Assignments