🖥️ Explore 20 hands-on experiments to master RISC-V computer architecture concepts using the Ripes simulator for effective learning.

Trace-driven cache memory simulator with LRU, MRU, RR and Belady replacement policies.

Exerting coherency between caches with protocols in a Memory-Shared Multiprocessors system whether it has uniform memory access(UMA, symmetric) or not(non-UMA).

Resources for CSARCH2 (Computer Organization and Architecture 2) to help students prepare for exams and build a strong foundation in computer architecture.

GoCache – High-Performance In-Memory Cache for Go

"vcache" is a library that provides a concurrent-safe in-memory cache to store key-value pairs.

CacheMap is a full-stack CPU cache simulator combining Python, Verilog, and DevOps with Docker, GitHub Actions, Nginx, Pytest, Prometheus, and Grafana.

A curated collection of RISC-V assembly experiments for the Ripes simulator — the repository provides ready-to-run labs that illustrate key CPU design and performance concepts. Each experiment comes with explained theory, .asm code, and expected metrics, making it ideal as a learning resource or teaching toolkit.

A modular and fully synthesizable 3-level (L1/L2/L3) cache memory subsystem implemented in SystemVerilog, featuring split L1 caches, a centralized L2, and a Last-Level L3 cache with coherence support.

The task is to design a "family" of three microprocessors that differ in performance and cost for the same computational task, as a project in "Computer Architecture 2" course.

This project is an implementation of cache memory with load and store instructions in Verilog.

Configurable Cache Memory Subsystem with Complete RTL-to-GDSII Implementation using OpenROAD.

Global News is designed to provide users with easy access to global news in a seamless and user-friendly manner. The app focuses on delivering a smooth user experience while ensuring that users can easily find and read news articles relevant to their interests and location.

A real-time Redis monitoring dashboard with interactive charts and metrics visualization.

Um programa que simula o referenciamento do endereço da memória principal na memória cache.

ASP.NET Core (.NET 6) Web API + cache (Redis, Memory)

ML-driven cache miss profiler that learns how your program touches memory across runs and rewires heap allocations to fix it. zero source changes, zero recompilation. Just wrap your command and let it learn.

RAM and cash memory emulation

Cache memory management project. Technologies and languages used: C++. University. Computer Structure.

A simulator of cache system behavior.