a high performance library for building cache simulators

Trace-driven cache memory simulator with LRU, MRU, RR and Belady replacement policies.

CPU Cache Simulation using gem5

This is a simulator for access strategies for distributed caching. The simulator considers a user who is equipped by several caches, and receives from them periodical updates about the cached content. The problem and algorithms implemented here are detailed in the paper: I. Cohen, G. Einziger, R. Friedman, and G. Scalosub, “Access Strategies for…

CLI-based OS memory management simulator with physical allocation, buddy system, cache hierarchy, and virtual memory

Cache Simulator with C++ langauge

A C++11 Based CDN cache simulator

This C project is a cache simulation of a CPU containing L1D, L1I and L2 caches. It takes an image of memory and a memory trace as input, simulates the hit/miss behavior of a cache memory on this trace, and outputs the total number of hits, misses and evictions for each cache type along with the content of each cache at the end.

This repository demonstrates basic HTTP caching techniques in a Node.js Express server, including the use of Cache-Control headers and ETag for efficient API responses.

Simulation study of cache architecture tradeoffs under concurrency — partitioned vs LRU vs client affinity, with trace-driven evaluation on Twitter cache workloads

Simulates MoE expert placement across GPU memory, RAM, and NVMe.

MIPS-style CPU simulator in Python supporting arithmetic, branching, memory ops, jump-and-link, cache simulation, and visual register/memory output.

gem5-based simulation study of Matrix–Matrix Multiplication (MM) across CPU models, clock frequencies, and memory hierarchies (DDR3/DDR4/DDR5). Includes config scripts, automation, stats collection, plots, and final report.

Contains all my coursework done for Computer Architecture course at IITH

Cache simulation in order to obtain performance metrics

2025-1 컴퓨터시스템개론: From Bit Manipulation to Cache Simulation

C++ based OS Memory Management Simulator demonstrating dynamic memory allocation and cache behavior.