🖥️ Explore 20 hands-on experiments to master RISC-V computer architecture concepts using the Ripes simulator for effective learning.

SEP, for Simple Enough Processor, is an elaborated from scratch simulated (on Logisim) educational CPU

A curated collection of RISC-V assembly experiments for the Ripes simulator — the repository provides ready-to-run labs that illustrate key CPU design and performance concepts. Each experiment comes with explained theory, .asm code, and expected metrics, making it ideal as a learning resource or teaching toolkit.

Microarchitecture impact analysis using gem5 - Computer Architecture course project - Computer Science @ FAMAF (UNC)

An 8-bit CPU designed in ModuleSim capable of executing 16 instructions fetched from a memory built with fundamental architectural modules supporting branching and prefix logics

Simple Processor Simulation

University computer-architecture project exploring low-level system and processor concepts.

MIPS-style CPU simulator in Python supporting arithmetic, branching, memory ops, jump-and-link, cache simulation, and visual register/memory output.

Out-of-order processor pipeline simulator with configurable ROB, IQ, and dispatch width

Procesor ve VHDL pro jazyk Brainfuck

Forth translator & CISC processor model