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axi4-lite-interface

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Here are 7 public repositories matching this topic...

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All 7 SystemVerilog 4 VHDL 1 Verilog 1

arhamhashmi01 / Axi4-lite

Star 27

This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.

systemverilog hardware-designs verilator axi4-lite axi4-protocol vivado-simulator axi4-lite-interface
  • Updated May 4, 2024
  • SystemVerilog

dpretet / meduram

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Star 13

Multi-port BRAM IP for ASIC and FPGA

block asic fpga ram yosys iverilog fusesoc bram amba axi4 axi4-lite multi-port svut axi4-lite-interface
  • Updated Apr 21, 2021
  • SystemVerilog

Ammar-Bin-Amir / AXI4

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RTL Design of AXI4 Bus Protocol followed by AXI4-Lite Bus Protocol and Handshaking Communication Principle

verilog axi4 rtl-design bus-protocol axi4-lite-interface handshaking-algorithm
  • Updated Apr 7, 2024
  • Verilog

muhammadtalhasami / Axi4_lite_interface

Star 3

This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .

vivado system-verilog verilator axi4 axi4-lite axi4-protocol axi4-lite-interface axi4-lite-system-verilog
  • Updated May 4, 2024
  • SystemVerilog

Arjun378 / aes256-crypto-riscv-soc

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AES-256 Hardware Accelerator SoC on Spartan-7 FPGA — RTL Design, UVM Verification, AXI4-Lite Integration, MicroBlaze V (RISC-V) SoC — Closed Timing at 125MHz

fpga verification aes-256 systemverilog vlsi uvm risc-v aes-256-ctr aes-256-cbc hardware-security axi4-lite vlsi-design aes-256-ecb rtl-design axi4-lite-interface
  • Updated Jul 4, 2026

talhaturac / zynq-hardware-timestamp-unit-linux

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ZynqMP 64-bit Hardware Timestamp Unit & Kernel Integration

zynq petalinux zybo embedded-linux hardware-timestamping ip-core zybo-z7 zynq-7020 axi4-lite-interface
  • Updated Apr 18, 2026
  • VHDL

sbaldzenka / axi_gpio

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GPIO IP-core with AXI4-Lite bus interface.

gpio fpga rtl systemverilog modelsim fpga-soc testbench axi4-lite axi4-protocol axi4-lite-interface
  • Updated Aug 21, 2026
  • SystemVerilog

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