FazBrowse GitHub Viewer | Trending |
URL:
| Home
Tools: [Download Repo ZIP]   [Original HTTPS Page]

axi4 · GitHub Topics · GitHub

Explore Topics Trending Collections Events GitHub Sponsors
#

axi4

Star

Here are 105 public repositories matching this topic...

Language: All
Filter by language
All 105 SystemVerilog 42 Verilog 23 Scala 8 C++ 7 Tcl 7 VHDL 6 Python 2 TypeScript 2 C 1 SMT 1
Sort: Most stars
Sort options
Most stars Fewest stars Most forks Fewest forks Recently updated Least recently updated

pulp-platform / axi

Star 1.7k

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

asic fpga hardware rtl ip systemverilog axi network-on-chip axi4 axi4-lite
  • Updated Aug 27, 2026
  • SystemVerilog

chipsalliance / Cores-VeeR-EH1

Star 965

VeeR EH1 core

fpga processor riscv rtl risc risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design veer
  • Updated Jul 16, 2026
  • SystemVerilog

taichi-ishitani / tvip-axi

Sponsor
Star 474

AMBA AXI VIP

vip systemverilog uvm axi amba axi4 amba-axi
  • Updated Jun 28, 2024
  • SystemVerilog

Hanley-Yao / Zynq7010_eink_controller

Star 432

这是一个基于Zynq7010的Eink控制器 在ED097TC2上高质量显示帧数高达10FPS

fpga zynq controller verilog eink axi4 fdma
  • Updated Aug 13, 2023
  • C

chipsalliance / Cores-VeeR-EL2

Star 344

VeeR EL2 Core

fpga processor riscv rtl risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design el2
  • Updated Aug 28, 2026
  • SystemVerilog

dpretet / axi-crossbar

Sponsor
Star 241

Parametric AXI4 crossbar in SystemVerilog

arm asic fpga processor riscv verilog soc fpga-soc interconnect amba crossbar riscv32 axi4 axi4-lite riscv64 monodraw axi4-protocol asic-design axi4-full
  • Updated May 25, 2026
  • SystemVerilog

WangXuan95 / FPGA-DDR-SDRAM

Star 222

An FPGA-based DDR1 controller. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。

fpga controller rtl verilog soft-core axi4 ddr-sdram ddr1
  • Updated Sep 15, 2023
  • Verilog

taichi-ishitani / tnoc

Sponsor
Star 211

Network on Chip Implementation written in SytemVerilog

systemverilog uvm noc axi amba network-on-chip axi4 amba-axi
  • Updated Aug 27, 2022
  • SystemVerilog

aignacio / ravenoc

Star 197

RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

router mpsoc noc network-on-chip axi4 flits virtual-channels
  • Updated Nov 18, 2024
  • SystemVerilog

OSVVM / AXI4

Sponsor
Star 157

AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

simulation vhdl verification vip tlm testbench osvvm simulation-modeling axi4 axi4-lite axi4-stream verification-component
  • Updated Aug 21, 2026
  • VHDL

loykylewong / FPGA-Application-Development-and-Simulation

Star 136

《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).

fpga i2c chisel verilog spi fft uart systemverilog dds digital-signal-processing iir fir modelsim modulation qam cordic cic i2s axi4 adpll
  • Updated Aug 18, 2026
  • Scala

mmxsrup / axi4-interface

Star 108

AXI4 and AXI4-Lite interface definitions

fpga systemverilog axi4 axi4-lite axi4-stream
  • Updated Sep 20, 2020
  • SystemVerilog

ultraembedded / core_sdram_axi4

Sponsor
Star 108

SDRAM controller with AXI4 interface

fpga verilog sdram-controller axi4
  • Updated Aug 8, 2019
  • C++

ultraembedded / core_ft60x_axi

Sponsor
Star 104

FTDI FT600 SuperSpeed USB3.0 to AXI bus master

fpga data-acquisition verilog bus-master ftdi-devices usb3 xilinx-fpga axi4 ft600
  • Updated Jun 6, 2020
  • C++

ultraembedded / core_dvi_framebuffer

Sponsor
Star 87

Minimal DVI / HDMI Framebuffer

video fpga verilog framebuffer hdmi dvi xilinx-fpga axi4
  • Updated Aug 9, 2020
  • Verilog

ultraembedded / core_dbg_bridge

Sponsor
Star 78

UART -> AXI Bridge

fpga verilog uart axi4
  • Updated Jul 1, 2021
  • Verilog

airhdl / spi-to-axi-bridge

Star 55

An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.

vhdl spi systemverilog axi4
  • Updated Dec 6, 2023
  • VHDL

ultraembedded / core_spiflash

Sponsor
Star 52

SPI-Flash XIP Interface (Verilog)

fpga verilog spi spi-flash xip axi4
  • Updated Oct 24, 2021
  • Verilog

ic-lab-duth / NoCpad

Star 41

HLS for Networks-on-Chip

hls noc high-level-synthesis network-on-chip cache-coherence axi4 axi4-lite
  • Updated Feb 18, 2021
  • C++

atfox272 / AXI4-Interconnect

Star 37

RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction.

axi interconnect axi4
  • Updated Mar 13, 2025
  • Verilog

Improve this page

Add a description, image, and links to the axi4 topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the axi4 topic, visit your repo's landing page and select "manage topics."

Learn more

Back | FazBrowse Home | New Git URL