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sdram-controller

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Here are 20 public repositories matching this topic...

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PrimeMHD / FPGA_ThreeLevelStorage

Star 120

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

fpga ddr verilog sd-card sdram-controller
  • Updated Jul 12, 2020
  • Coq

ultraembedded / core_sdram_axi4

Sponsor
Star 108

SDRAM controller with AXI4 interface

fpga verilog sdram-controller axi4
  • Updated Aug 8, 2019
  • C++

yigitbektasgursoy / SDRAM_Verilog

Star 49

Verilog HDL implementation of SDRAM controller and SDRAM model

verilog vivado verilog-hdl sdram sdram-controller verilog-project
  • Updated Jun 19, 2024
  • Verilog

AngeloJacobo / FPGA_SDRAM_Controller

Star 31

SDRAM controller optimized to a memory bandwidth of 316MB/s

fpga verilog sdram sdram-controller
  • Updated Aug 16, 2021
  • Verilog

Arkowski24 / sdram-controller

Star 14

Simple SDRAM Controller for DE10-Lite.

fpga verilog sdram sdram-controller
  • Updated Jan 20, 2019
  • Verilog

MinatsuT / CYC1000_SDRAM

Star 13

A sample design of Nios with on-board SDRAM for CYC1000 (a low cost Cyclone10 FPGA board)

fpga quartus-prime nios2 sdram sdram-controller cyclone-10lp cyc1000
  • Updated Jul 8, 2021
  • Verilog

cw1997 / SDRAM-Controller

Star 12

SDRAM Controller, written by SystemVerilogHDL, supporting passing parameters including CAS Latency(CL), burst mode enable and burst length, using writing and reading control signal as request/response handshake bus protocol

hardware systemverilog hardware-designs sdram sdram-controller verilog-project
  • Updated Jul 1, 2022
  • HTML

agg23 / sdram-controller

Sponsor
Star 12

A HDL SDRAM controller designed for retro hardware and FPGAs

fpga sdram sdram-controller misterfpga analogue-pocket
  • Updated Jun 25, 2023
  • SystemVerilog

jakubcabal / sdram-tester-fpga

Sponsor
Star 10

SDRAM Tester implemented in FPGA

python fpga vhdl sdram sdram-controller cyc1000 measures-throughput sdram-tester
  • Updated May 1, 2021
  • VHDL

egk696 / EDAC_SDRAM_Controller

Star 9

Mitigating Single-Event Upsets in COTS SDRAM using an EDAC SDRAM Controller

fpga vhdl embedded-systems vivado fault-tolerant quartus-prime sdram sdram-controller cots-sdram
  • Updated Oct 30, 2017
  • Verilog

ShwetaKiranTotla / Micro-processor-Design-Verification

Star 6

Design Verification of Flash, UART, and SDRAM controller for a 32 bit embedded RISC microprocessor using cocotb.

python flash makefile verification uart risc testbench sdram sdram-controller cocotb cocotb-testing design-verification
  • Updated Oct 15, 2023
  • Verilog

teekamkhandelwal / SRAM_Controller

Star 4

The Enhanced SRAM Controller handles secure, efficient memory operations with features like burst mode, error correction, power-saving, and clock domain crossing. It’s perfect for applications requiring robust and reliable memory handling.

memory verilog sram memory-management vivado questasim sdram sdram-controller memory-controller verilog-project vlsi-design sram-controller sram-controller-advanced sram-features-power-security-brust verlog-hdl enhanched-sram-controller
  • Updated Oct 21, 2024
  • Verilog

armleo / sdram_controller

Star 4

SDR SDRAM Controller with Avalon-MM bus

fpga verilog sdram sdram-controller
  • Updated Apr 11, 2022
  • Verilog

yasnakateb / SdramController

Star 3

🛠 A SDRAM controller in Verilog HDL

verilog icarus-verilog verilog-hdl iverilog sdram sdram-controller memory-controller
  • Updated Mar 21, 2022
  • Verilog

oskarwires / sdram_controller

Star 3

High-Speed SystemVerilog SDRAM Controller

fpga sdram sdram-controller
  • Updated Jan 27, 2024
  • SystemVerilog

kevin861222 / SDRAM_controller

Star 3

SDRAM controller

sdram-controller digital-ic-design
  • Updated Aug 15, 2024
  • Verilog

francisvalguedes / cyclone-fpga-riscv-sdram-pwm

Star 1

RISC-V (Nios V) SoC para placas genéricas Cyclone IV (EP4CE6, EP4CE10, EP4CE15) com controlador SDRAM, bootloader via SPI e módulo PWM (com Testbench) em VHDL

fpga vhdl fpga-soc risc-v cyclone-iv ep4ce6e22c8n nios-embedded-system sdram sdram-controller vhdl-examples vhdl-testbench pwm-controller ep4ce6 niosv ep4ce15 risc-v-processor quartus-prime-lite ep4ce6f17c8 ep4ce22 nios-v
  • Updated Aug 19, 2026
  • SystemVerilog

Dosang2108 / Sdram_Control-in-RV32-IMAC

Star 0
verilog riscv32 sdram-controller rv32im
  • Updated May 9, 2026
  • C

Nikhil-Ashok-Kumbhar / SDRAM-Controller-Design

Star 0

Overview: The goal of this project is to design an SDRAM controller that allows SDRAM memory to be interfaced with a microprocessor having only asynchronous memory support. There is no requirement to build the hardware, but a complete written report containing schematics and theory of operation is required

sdram-controller
  • Updated Oct 10, 2020

GCDPrasad / MINI_PROJECT

Star 0

DESIGN AND IMPLEMENTATION OF 64-BIT SRAM AND SDRAM POWER OPTIMIZED CONTROLLER

sram sdram-controller
  • Updated Mar 21, 2026

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