Opensource DDR3 Controller

A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs

mirror of https://git.elphel.com/Elphel/eddr3

UEFI memory diagnostic tool - 14 stress tests, per-chip stuck-bit mapping, MCA capture, marathon mode, plain-language verdict with DIMM warranty info

This is not Linux kernel maintainer's tree, but an open-source work in progress. Officially maintained repositories are under kernel.org (Samsung SoC, memory controller drivers etc.).

Multi-Channel DDR Memory Controller Design with BFM-Based Verification and UVM-Style Testbench

A bare-metal SRAM memory controller suitable for Xilinx FPGAs.

The Enhanced SRAM Controller handles secure, efficient memory operations with features like burst mode, error correction, power-saving, and clock domain crossing. It’s perfect for applications requiring robust and reliable memory handling.

SystemVerilog and UVM verification of an 8x8 SRAM memory controller with coverage, scoreboard, regression scripts, and bug-demo dashboard.

🛠 A SDRAM controller in Verilog HDL

This repository contains a JEDEC-style DDR2 SDRAM controller targeting the memory devices. The controller exposes a simple FIFO-like front-end interface and maps host commands into DDR2 transactions, including full power-up initialization, periodic refresh, scalar and block reads/writes, and DQS-based data capture.

Xilinx UltraScale+ based HyperBus controller for HyperRam memories

Industrial asynchronous dual-port RAM subsystem in Verilog with CDC synchronizers and AXI-style handshake interface.

This repository contains a JEDEC-style DDR2 SDRAM controller targeting the memory devices. The controller exposes a simple FIFO-like front-end interface and maps host commands into DDR2 transactions, including full power-up initialization, periodic refresh, scalar and block reads/writes, and DQS-based data capture.

DDR memory controller implementation and verification

HBM4 System Modeling Platform - High Bandwidth Memory simulation and verification framework

Behavioral architecture of a read/write cycle controller for a DRAM chip.

Advanced SRAM Controller with ECC Support for Sky130 Process - Production-Ready Multi-Port Memory System.

Architectural RTL prototype of an HBM-style memory subsystem (controller, interleaving, ECC, power states).

In this repository, I have published my knowledge gained while working on FIFO Project implementation using Verilog, System Verilog, UVM