A dynamic verification library for Chisel.

Python packages providing a library for Verification Stimulus and Coverage

Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)

Python API to Unified Coverage Interoperability Standard (UCIS) Data

This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.

UART verification using UVM with functional coverage, scoreboard, and test scenarios, simulated on QuestaSim.

Configurable AXI4 Verification IP developed using UVM, featuring reusable master and slave agents, protocol checking, functional coverage, and scoreboard-based verification.

RV32IM RISC-V CPU core with a full UVM verification environment and ISA-compliance via Spike (DPI-C): constrained-random, SVA, coverage, Python debug tools, and CI.

Simple and Complete UVM TestBench For Verification Of S R Latch

Pure-Python RISC-V instruction generator with built-in functional coverage, auto-regression, and CI-ready dashboards.

UVM-based SystemVerilog testbench for CDC & Async FIFO: SVA assertions, functional coverage, agents/sequences/scoreboard, and VCS/Questa run scripts.

SystemVerilog and UVM verification of an 8x8 SRAM memory controller with coverage, scoreboard, regression scripts, and bug-demo dashboard.

UVM-based verification of an AHB-to-APB bridge, validating protocol compliance, address decoding, data integrity, error handling, and corner cases using constrained-random testing and functional coverage.

UVM-based verification environment for a 5-stage RV32I RISC-V pipeline using constrained-random testing, DPI-C golden reference modeling, assertions, scoreboarding, functional coverage, and 20-seed QuestaSim regression debugging.

Hands-on Design Verification — SystemVerilog testbenches, full UVM environment for APB Protocol, Python scripting, SVA assertions & functional coverage. Trained at ChipEdge using Synopsys VCS.

UVM verification environment for an I2C controller (constrained-random + assertions + functional coverage) — Questa/ModelSim

Custom 16-bit 3-stage pipelined CPU in SystemVerilog with UVM verification, RAW hazard handling, assertions, constrained-random testing, and functional coverage.

Complete UVM TestBench For Verification Of Ring (Onehot) Counter

AHB to APB Bridge Design and UVM-based Verification as per AMBA specifications.

A 4x4 INT8 output-stationary MAC array in SystemVerilog, verified with a from-scratch UVM 1.2 environment - constrained-random stimulus, reference-model scoreboard, SVA, functional coverage, and Python-driven regression.