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directed-testing

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All 4 SystemVerilog 3 Python 1

Entropify / Entropic_R32-P5_RISC-V

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5-Stage Pipelined RISC-V CPU utilizing the RV32I ISA, featuring dynamic branch prediction. Designed, verified, performance tested, and ASIC-flowed

asic gcc verilog systemverilog hazard-detection performance-testing risc-v branch-prediction rv32i gdsii cpu-architecture cocotb forwarding-unit rtl-design riscv-assembly 5-stage-pipeline pipelined-processor directed-testing rtl-verification openlane2
  • Updated Aug 29, 2026
  • Python

abdo-ehab-euv / sram-controller-uvm-verification

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SystemVerilog and UVM verification of an 8x8 SRAM memory controller with coverage, scoreboard, regression scripts, and bug-demo dashboard.

python tcl verification rtl scoreboard sram regression-testing systemverilog modelsim uvm testbench constrained-random memory-controller questa hardware-verification functional-coverage uvm-verification directed-testing design-verification-project
  • Updated May 14, 2026
  • SystemVerilog

Rex1110 / AES-128

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SystemVerilog implementation of AES-128 encryption and decryption , designed for resource efficiency

aes rtl aes-128 systemverilog assertion sva constrained-random-verification directed-testing
  • Updated Jan 30, 2025
  • SystemVerilog

nbathula16 / SV-Project

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32-bit Single Precision Floating point Multiplication

coverage randomization constraint floating-point testbench normalization multiplier conditional-compilation directed-testing
  • Updated Mar 23, 2023
  • SystemVerilog

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