Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.

RTL data structure

Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀

Systemverilog and UVM exercises inspired by ziglings

Configurable AXI4 Verification IP developed using UVM, featuring reusable master and slave agents, protocol checking, functional coverage, and scoreboard-based verification.

Synthesizable AXI4 crossbar with a full UVM verification environment — RTL, SVA, coverage, stress, and CI.

Multi-Channel DDR Memory Controller Design with BFM-Based Verification and UVM-Style Testbench

Sapphire SoC: RV32I RISC-V core optimized for FPGAs, featuring UVM verification, AXI4-Lite bus, FreeRTOS support, and Shakti-inspired design. Open-source under MIT license for embedded/IoT applications.

BDD Gherkin implementation in native SystemVerilog, based on UVM.

Getting started with SystemVerilog: Hardware Description Language for design and verification.

RISC-V processor co-simulation using SystemVerilog HDL and UVM.

This repository is meant for learning UVM using SystemVerilog. Through a verification environment, some hardware verification concepts are applied for a calculator with the four basic operations.

A UVM-based verification environment for a multi-core, write-back L2 cache on 32-bit RISC-V, enforcing MESI coherence with L1 caches and interfacing to DRAM over AXI4-Lite.

Router 1 x3 is a Basic level Design of Wireless Fidelity Router Model • The top level consists of 4 blocks-3 FIFO{First In First Out Register) , 1 Register, 1 Synchroniser and 1 Control Block (FSM-Finite State Machine) • RTL and Testbench are coded in verilog and the waveforms are generated using Modelsim software. • The Synthesis was performed u

A synthesizable Gigabit Ethernet MAC IP core with full UVM verification environment.

An FPGA implementation of Cummings' Asynchronous FIFO

A parameterizable Systolic Array Hardware Accelerator for CNNs implemented in SystemVerilog, optimized for high-throughput Matrix-Matrix Multiplications (GEMM) with an RTL-to-GDSII flow.

Verification of Advanced Encryption Standard (AES-128) Using the Universal Verification Methodology (UVM).

This project uses UVM to verify an SPI Slave connected to internal RAM. It includes multiple agents (active and passive) and integrates assertion-based verification for both SPI and RAM behavior.