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sdram

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ultraembedded / cores

Sponsor
Star 932

Various HDL (Verilog) IP Cores

audio asic fpga usb rtl verilog spi sram uart verilog-hdl verilog-components verilator i2s sdram
  • Updated Jul 1, 2021
  • Verilog

1a2m3 / SPD-Reader-Writer

Star 190

SPD Reader & Writer with Software Write Protection capabilities supporting Arduino and SMBus

windows arduino amd ddr intel nvidia smbus spd eeprom-programmer eeprom-reader sdram ddr3 ddr4 ddr2 spd-reader spd-writer ddr5 rswp
  • Updated Jun 23, 2024
  • C#

nullobject / sdram-fpga

Star 126

A FPGA core for a simple SDRAM controller.

fpga controller memory sdram
  • Updated Nov 13, 2021
  • VHDL

hdl-util / sdram-controller

Star 86

Generic FPGA SDRAM controller, originally made for AS4C4M16SA

fpga controller systemverilog dram quartus sdram as4c4m16sa
  • Updated Sep 7, 2020
  • Verilog

jasonsbeer / Amiga-N2630

Star 68

A re-imagining of the Amiga A2630 processor card.

unix motorola accelerator ide amiga commodore amigaos coprocessor sdram pata 2000 68030 amix amigados a2630 68882
  • Updated Nov 1, 2025
  • KiCad Layout

yigitbektasgursoy / SDRAM_Verilog

Star 49

Verilog HDL implementation of SDRAM controller and SDRAM model

verilog vivado verilog-hdl sdram sdram-controller verilog-project
  • Updated Jun 19, 2024
  • Verilog

ghent360 / riscvOnColorlight-5A-75B

Star 44

RISC-V soft core running on Colorlight 5B-74B.

fpga riscv risc-v litex sdram ecp5 colorlight lattice-fpga 5a-75 5a-75b ehternet
  • Updated Feb 14, 2021
  • C

AngeloJacobo / FPGA_SDRAM_Controller

Star 31

SDRAM controller optimized to a memory bandwidth of 316MB/s

fpga verilog sdram sdram-controller
  • Updated Aug 16, 2021
  • Verilog

iliasam / stm32f429_vga_examples

Star 25

Code examples of using STM32F429 for generating VGA image.

sdio sdram dcmi stm32f429 ltdc
  • Updated Apr 29, 2023
  • C

machdyne / kuchen

Star 23

Kuchen Computer

fpga usb computer hdmi ice40 sdram ice40hx8k computer-hardware
  • Updated Jun 26, 2024
  • OpenSCAD

oscc-ip / sdram

Star 22

An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different manufacturers and models through parameter configuration.

fpga verilog sdram axi4 tapeout
  • Updated May 12, 2025
  • Scala

qubeck78 / tangerineA7_200

Star 21

RiscV based SOC for Qmtech Artix A7-200 board. Includes nekoRv: RISC-V 32 IM Zicsr core. And yes, it runs DOOM :)

vhdl riscv hdmi sdram
  • Updated Jan 13, 2025
  • VHDL

maojinxiang / FPGA-ANLU-National-First-Prize

Star 18

2025年全国大学生嵌入式芯片与系统设计竞赛 FPGA创新设计赛道 安路二赛题 国家级一等奖

python fpga udp image-processing embedded-systems verilog ethernet hdmi ov5640 sdram anlogic rgmii
  • Updated Jul 20, 2026
  • Verilog

perehinik / SDRAM_Controller

Star 17

Verilog SDR SDRAM controller for FPGA Xilinx and Lattice

fpga verilog xilinx lattice sdram
  • Updated Jan 3, 2021
  • VHDL

har-in-air / SIPEED_TANG_PRIMER

Star 17

Projects using the Sipeed Tang Primer FPGA development board

fpga ov7670 sdram sipeed-tang-primer audio-crossover
  • Updated Dec 6, 2020
  • Verilog

andrempmattos / harsh-payload

Star 17

Harsh Environment CubeSat Payload designed to evaluate three different manufacturing nodes SDR SDRAM technologies under space radiation conditions. It was developed for the FloripaSat-2 CubeSat mission.

fpga freertos smartfusion2 sdram armcortexm3 cubesat-payload m2s010 m2s025 radiation-experiment spacelab-ufsc
  • Updated Sep 7, 2021
  • VHDL

Arkowski24 / sdram-controller

Star 14

Simple SDRAM Controller for DE10-Lite.

fpga verilog sdram sdram-controller
  • Updated Jan 20, 2019
  • Verilog

MinatsuT / CYC1000_SDRAM

Star 13

A sample design of Nios with on-board SDRAM for CYC1000 (a low cost Cyclone10 FPGA board)

fpga quartus-prime nios2 sdram sdram-controller cyclone-10lp cyc1000
  • Updated Jul 8, 2021
  • Verilog

agg23 / sdram-controller

Sponsor
Star 12

A HDL SDRAM controller designed for retro hardware and FPGAs

fpga sdram sdram-controller misterfpga analogue-pocket
  • Updated Jun 25, 2023
  • SystemVerilog

cw1997 / SDRAM-Controller

Star 12

SDRAM Controller, written by SystemVerilogHDL, supporting passing parameters including CAS Latency(CL), burst mode enable and burst length, using writing and reading control signal as request/response handshake bus protocol

hardware systemverilog hardware-designs sdram sdram-controller verilog-project
  • Updated Jul 1, 2022
  • HTML

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