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axi-bus

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Here are 8 public repositories matching this topic...

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All 8 VHDL 4 Verilog 2 HTML 1 SystemVerilog 1

ZipCPU / wb2axip

Star 699

Bus bridges and other odds and ends

fpga gplv3 xilinx wishbone xilinx-vivado wishbone-bus axi-bus
  • Updated Jun 2, 2026
  • Verilog

Zhaoyang-Liang / pipline_cpu_with_Cache-TLB

Star 9

CPU , 5-stage pipelined , with cache(I/D), TLB, and AXI interface implemented in Verilog. 五级流水线 MIPS CPU，支持前递、异常中断、TLB、缓存和 AXI 总线接口

simulator cpu pipeline cache verilog tlb axi cpu-simulator axi-bus
  • Updated Mar 10, 2026
  • Verilog

mnemocron / axi-perf-counter-pattern

Star 2

Performance counter to measure latency between two AXI Stream interfaces with pattern matching as trigger.

vhdl performance-analysis axi-bus axi-stream axi4 latency-analysis
  • Updated Aug 3, 2023
  • VHDL

DarrenHuang0411 / Verilog-Training-AXI-bus

Star 2

5-stage-Pipeline-CPU with AXI bus

systemverilog vlsi system-design axi-bus vlsi-design
  • Updated Nov 7, 2024
  • SystemVerilog

GhlHub / hyperbus_controller

Star 2

Xilinx UltraScale+ based HyperBus controller for HyperRam memories

fpga memory xilinx axi-bus memory-controller hyperram hyperbus
  • Updated Apr 21, 2026
  • VHDL

vacagonzalo / soc-workflow-vhdl

Star 1

Example workflow project for VHDL development.

workflow vhdl tcl vivado axi axi-bus tcl-scripts cocotb cocotb-testing
  • Updated Feb 18, 2023
  • VHDL

marchese / aximemcomp

Star 0

This is a hardware project of an inline memory compressor that reduces the amount of memory used by embedded systems

arm fpga hardware vhdl tcl verilog compressor axi-bus zynq-7000
  • Updated May 8, 2018
  • VHDL

ropy-irishterrier524 / esports-odds-bet-analyzer

Star 0

Compare e-sports betting lines in the browser with match context and probability-focused insights.

nodejs scraper typescript spritesheet html5-game web-scraping strategy-game multiplayer-browser-game sports-stats hacktoberfest 2d-game odds xilinx-vivado axi-bus turn-based-strategy playwright oddsportal
  • Updated Aug 28, 2026
  • HTML

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