Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.

simple verilog digital circuits sampels (halfAdder, fullAdder, ALSU , ...)

A 32-bit Kogge-Stone Adder is implemented in this design.

LTSpice simulation software is used to study the behavior of a Memristor. Different logic gates like NOR, NAND and XOR were modelled and simulated followed by the simulation of a memristor based full-adder.

This project was performed on the completion of our B. Tech 4th Semester Summer Training cum Academic Internship Programme on "RISC-V based 32-bit Digital Processor Design using SPICE" under E&ICT Academy IIT Guwahati and Assam Science & Technology University, Guwahati under TEQIP III in association with VLSI Expert

These are VHDL codes for a signed 4bit multiplier using 4bit adders. Base on Baugh-Wooley Method.

This is a VHDL code for 4bit multiplier using 4bit full adder circuit structurally modelled.

A DIY 8 Bit Adder from single transistors

Digital Logic Design using pen and paper to design with Analog discovery 2, and using Verilog for synthesizing. these are some of my junior year labs for Digital Electronics

4-bit Serial Adder/Subtractor with Parallel Load

4 bit ALU in verilog

A project that simulate the circuits FullAdder and FullSubtractor

Digital Design using Verilog

one cycle unsigned multiplier, don't cares of resources fpga or asic structures

➕➕ Arithmetic operations in most machines are performed in the ALU whereby logic gates and flipflops are combined so that they can subtract, multiply, and divide binary numbers. This circuit only implements the addition part, on four bit digits

Simulation of full adder circuit to add two byte-sized integers in Python 3.

CMOS Full Adder design using Cadence Virtuoso including schematic design, simulation and layout verification (DRC, LVS REX).

1-bit CMOS full adder, hand-laid in Glade on the C5N 0.5 µm PDK , DRC/LPE/LVS tested