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An open-source static random access memory (SRAM) compiler.
A flexible framework for analyzing and transforming FPGA netlists. Official repository.
SPICE netlist visualizer
A MATLAB project that uses modified nodal analysis to calculate the node voltages of any analog circuit.
TMR utilities for the SpyDrNet project
A low-level hierarchical netlist assembler for FPGAs
SKiDL Microcontroller Board Wizard
This repository will include projects and solutions to problems solved and verified with Spice.
Counter with two guardians who count each bit either even or odd.
CAD Tools — (Course: CAD Tools, Semester 8): lab exercises written in C creating a tool for SPICE simulation and architecture output with step-by-step reports and project files.
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