Open-source high-performance RISC-V processor

Chisel: A Modern Hardware Design Language

Rocket Chip Generator

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

SonicBOOM: The Berkeley Out-of-Order Machine

Simple RISC-V 3-stage Pipeline in Chisel

Work in progress prototype for the Chisel Level Editor, for Unity

RISC-V 32bit single-cycle CPUs written in Logisim, Verilog, and Chisel

A .NET XOR encrypted cobalt strike aggressor implementation for chisel to utilize faster proxy and advanced socks5 capabilities.

Modern tunnel management built on GOST, Backhaul, FRP, Chisel and Rathole, featuring an intuitive WebUI, fast CLI, and open-source freedom.

All-in-one OPIran scripts

A 3D FPGA GPU for real-time rasterization with a tile-based deferred rendering (TBDR) architecture, featuring transform & lighting (T&L), back-face culling, MSAA anti-aliasing, ordered dithering, etc.

Establish a Reverse Tunnel between different servers and clients. IPV4 | IPV6 - Supports TCP & UDP . You can establish a tunnel between 5 Kharej servers & 1 IRAN server and vice versa.

A Chisel RTL generator for network-on-chip interconnects

The batteries-included testing and formal verification library for Chisel-based RTL designs.

A compact guide to network pivoting for penetration testings / CTF challenges.

Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel

high-performance RTL simulator

A tool to create HTTPS reverse tunnels

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.