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Verilog

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Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.

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logisim-evolution / logisim-evolution

Star 7.6k

Digital logic design tool and simulator

education simulator fpga vhdl logic circuits verilog circuit digital-logic logisim digital-circuit digital-circuits timing-diagram digital-logic-design logisim-evolution
  • Updated Sep 22, 2026
  • Java

LeiWang1999 / FPGA

Star 5.8k

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

fpga verilog xilinx vivado pynq
  • Updated May 15, 2022

open-sdr / openwifi

Star 4.8k

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

linux fpga zynq hls hardware wifi verilog xilinx sdr analog-devices ieee80211 xilinx-fpga dma software-defined-radio ofdm csma ad9361 802-11 mac80211 openwifi
  • Updated Sep 21, 2026
  • C

chipsalliance / chisel

Star 4.8k

Chisel: A Modern Hardware Design Language

scala chip-generator chisel rtl chisel3 firrtl verilog
  • Updated Sep 22, 2026
  • Scala

verilator / verilator

Star 3.9k

Verilator open-source SystemVerilog simulator and lint system

cpp rtl verilog compilers systemc system-verilog verilator verilog-simulator
  • Updated Sep 22, 2026
  • SystemVerilog

SpinalHDL / VexRiscv

Star 3.3k

A FPGA friendly 32 bit RISC-V CPU implementation

cpu fpga vhdl riscv verilog soc spinalhdl softcore
  • Updated Sep 19, 2026
  • Assembly

The-OpenROAD-Project / OpenROAD

Star 3.1k

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

cpp tcl eda rtl verilog def gdsii timing-analysis openroad lef opendb-database
  • Updated Sep 22, 2026
  • Verilog

SI-RISCV / e200_opensource

Star 2.9k

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

cpu core verilog china nuclei risc-v ultra-low-power
  • Updated Mar 24, 2021
  • Verilog

darklife / darkriscv

Star 2.6k

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

fpga core riscv verilog risc-v
  • Updated Sep 4, 2026
  • Verilog

cocotb / cocotb

Star 2.5k

cocotb: Python-based chip (RTL) verification

python test vhdl verification verilog uvm
  • Updated Sep 22, 2026
  • Python

stnolting / neorv32

Star 2.3k

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

microcontroller asic cpu fpga processor vhdl verilog soc risc-v soft-core
  • Updated Sep 20, 2026
  • VHDL

jbush001 / NyuziProcessor

Star 2.2k

GPGPU microprocessor architecture

processor-architecture fpga hardware gpu graphics verilog microprocessor gpu-computing
  • Updated Nov 8, 2024
  • C

SpinalHDL / SpinalHDL

Star 2k

Scala based HDL

scala fpga vhdl rtl verilog
  • Updated Sep 19, 2026
  • Scala

pConst / basic_verilog

Star 2k

Must-have verilog systemverilog modules

spi-interface fpga hls encoder delay tcl verilog debounce xilinx synchronizer uart altera uart-verilog fifo pwm uart-protocol spi-master uart-controller uart-tx uart-receiver
  • Updated Mar 12, 2026
  • Verilog

analogdevicesinc / hdl

Star 2k

HDL libraries and projects

fpga verilog hdl hacktoberfest analog-devices jesd204b
  • Updated Sep 22, 2026
  • Tcl

The-OpenROAD-Project / OpenLane

Star 1.9k

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

magic asic rtl verilog vlsi foundry yosys klayout caravel netgen system-on-chip openroad openram skywater 130nm soc-design rtl2gds
  • Updated Mar 25, 2026
  • Python

FPGAwars / icestudio

Star 1.9k

❄️ Visual editor for open FPGA boards

javascript editor fpga ide blocks verilog icestorm lattice icestudio
  • Updated Aug 21, 2026
  • JavaScript

riscv-mcu / e203_hbirdv2

Star 1.9k

The Ultra-Low Power RISC-V Core

cpu fpga core riscv verilog china hummingbird nuclei soc risc-v low-power e203
  • Updated Aug 6, 2025
  • Verilog

google / xls

Star 1.9k

XLS: Accelerated HW Synthesis

open-source compiler hls pipeline verilog high-level-synthesis mid-level-synthesis
  • Updated Sep 22, 2026
  • C++

olofk / serv

Star 1.9k

SERV - The SErial RISC-V CPU

asic fpga verilog risc-v
  • Updated Aug 25, 2026
  • Verilog
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