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Modular hardware build system
Education kit for teaching VLSI fundamentals through practical microprocessor design using industry EDA tools (educational)
55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd. (ICS55 for short).
A browser-based SPICE circuit simulator
Kho tài liệu đi từ nền tảng Điện tử căn bản đến Thiết kế vi mạch, tập trung vào Front-End (RTL/DV). Tích hợp kiến thức bổ trợ cho các hướng công việc khác thuộc chuyên ngành Điện Tử. Biên soạn bởi Minh Ú (Phùng Quang Minh).
微电子和集成电路自学指南
The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout design is done using Cadence Virtuoso’s ADE, & the Static Noise Margin is obtained through Matlab scripts.
Home Brew 8 Bit CPU Hardware Implementation including a Verilog simulation, an assembler, a "C" Compiler and this repo also contains my research and learning. See also the Hackaday.IO project. https://hackaday.io/project/166922-spam-1-8-bit-cpu
Simple, self-contained, clean code, well-documented, hobbyist 64-bit operating system for Intel and AMD processors. It's written in Assembly (Intel syntax) and C (GNU99 Standard) in which I strive for adding comments to the source code so it could be used as a reference for future OS developers
8-bit combinational ALU built from scratch with 3,488 CMOS transistors (KiCad + SPICE + Logisim + 1.24M tests
This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.
axiom micro mainboard containing the cmos sensor, headers for plugin modules and more
Noise Correction Algorithm for sCMOS cameras
Building a computer from scratch using 74xx logic chips
NGSPICE Simulation of CMOS Circuits
All the projects and assignments done as part of VLSI course.
Home brew CPU Hardware with 1-bit ALU implementation using 74LSxx, a micro-code and assembler coded in C#.
This project shows how to design a clock bootstrapped circuit to improve the nonlinearity of the switch used in Track & Hold circuit. A comparison is done between several topologies, showing the ENOB, SNR, & SFDR achieved in each case.
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