Explore Topics Trending Collections Events GitHub Sponsors

xsim

Here are 15 public repositories matching this topic...

Language: All Sort: Most stars

wyvernSemi / pcievhost

PCIe (1.0a to 2.0) Virtual Root Complex model, in C, co-simulating with Verilog, SystemVerilog and VHDL, with Endpoint capabilities

c verification verilog virtual vivado modelling icarus-verilog ghdl cosim pcie pli bfm verilator nvc xsim questa-sim

Updated Jun 16, 2026
C

mapleleavessssssss-wq / vivado-mcp

Star

Vivado MCP server — 让 Claude Code / Cursor / Codex 驱动本地 FPGA 全流程。30 个精选工具、8 个证据驱动 Prompt、doctor 环境自检、GUI/Tcl/attach 会话，以及时序和 CRITICAL WARNING 中文诊断。

python ai fpga mcp tcl eda verilog xilinx vivado codex claude xsim model-context-protocol mcp-server hardware-debugging

Updated Aug 9, 2026
Python

wyvernSemi / usbModel

Star

USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL

usb vhdl verilog vivado systemverilog icarus-verilog ghdl nvc xsim cosimulation cmodel questa-sim

Updated Oct 15, 2024
C++

wyvernSemi / tcpIpPg

Star

10GbE XGMII TCP/IPv4 packet generator in C, co-simulating with Verilog, SystemVerilog and VHDL

simulation verification verilog vivado ethernet icarus-verilog ghdl tcp-ip verilator nvc 10g xsim virtual-processor xgmii questa-sim

Updated Jan 28, 2025
C++

mzh330521 / SublimeLinter-contrib-xsim

Star

Vivado Simulator (XSim) xvlog/xvhdl plugin for SublimeLinter. Linting for Verilog/SystemVerilog and VHDL.

sublime-text vhdl sublimelinter linter-plugin verilog systemverilog xsim vivado-simulator

Updated May 29, 2024
Python

Ross0907 / Vivado-waveform-extractor

Star

A TCL script to extract Vivado's xsim simulation data in the VCD format packaged with a VCD converter with multiple conversion options including exporting to excel and changing the radix.

python amd python-script vivado vcd tcl-scripts xsim vivado-simulator

Updated Dec 7, 2025
Python

RipperJ / VerilogExpr2NAND-NOR

Star

Logic Expression Compiler, with Logic Minimization, to NAND/NOR Implementation

compiler simulation lex espresso ply verilog yacc boolean-expression nand logic-minimization nor xsim vivado-simulator pyeda

Updated Jun 4, 2023
Python

Yucheng-art / rv32i-l1-cache-pipeline

Star

A verified four-stage RV32I pipeline with parameterized L1 instruction/data caches, XSim regression tests, and portable Vivado flows.

cpu fpga pipeline cache verilog vivado computer-architecture risc-v rv32i xsim

Updated Aug 6, 2026
Verilog

Raveem13 / axi-matrix-accelerator

Star

This project implements AXI-based matrix multiply accelerator.

accelerator verilog systemverilog hardware-designs hardware-acceleration axi xsim vivado-simulator hardware-accelerator uvm-verification matrix-multiply-accumulate ai-accelerator

Updated Aug 27, 2026
SystemVerilog

Raveem13 / VivadoXSIM-UVM_verification

Star

This repository showcases my hands-on SystemVerilog UVM verification using Xilinx Vivado XSIM, focusing on real-world RTL verification, debugging, coverage, and regression scenarios.

coverage-reports vivado systemverilog hdl asic-verification xsim vivado-simulator uvm-verification

Updated Mar 10, 2026
CSS

Project is a high-precision chronometer using VHDL, intended for implementation on an FPGA. The chronometer is designed to operate with nanosecond (ns) precision and is capable of accurately measuring elapsed time in milliseconds, seconds, and minutes. The design has been tested using a VHDL test bench and verified with the XSim extensively.

vhdl vivado xsim

Updated Jul 3, 2024
VHDL

marslan6 / Flex-PWM500

Star

The PWM (Pulse Width Modulation) Generator creates a PWM signal to control PWM-driven devices. It allows configurable clock and PWM frequencies via generics. The duty cycle, input as a 7-bit signal, adjusts the proportion of time the signal is high.

vhdl vivado testbench xsim vhdl-testbench