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mips-processor

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mhyousefi / MIPS-pipeline-processor

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A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding

pipeline verilog computer-architecture hazard-detection mips-processor forwarding-unit

Updated May 20, 2022
Verilog

neelkshah / MIPS-Processor

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5-stage pipelined 32-bit MIPS microprocessor in Verilog

verilog microprocessor computer-architecture microprocessors verilog-hdl mips-architecture mips-processor bits-pilani computer-organization verilog-components verilog-snippets mips-instructions computer-organisation verilog-programs verilog-simulator verilog-project

Updated Apr 3, 2020
Verilog

aeris170 / MARS-Theme-Engine

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It's all coming back into focus!

mips mips-assembly mars mips-architecture mips-processor mips-simulator mars-theme-engine

Updated May 11, 2024
Java

Ingenic-community / linux

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Linux kernel source tree with the latest features and modifications to unleash the full potential of Ingenic processors.

linux mips linux-kernel mips-architecture mips-processor mips32 x1000 jz4780 ingenic x2000 x1501

Updated Mar 27, 2025
C

alirezakay / RISC-CPU

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A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )

processor-architecture cpu vhdl isa cpu-model instruction-set-architecture mips-processor vhdl-modules risc-processor vhdl-code cpu-architecture multi-cycle processor-design

Updated Jun 19, 2021
VHDL

edoardottt / asm-snippets

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Some of my assembly code (examples, iterative and recursive algorithms) from Computer's Architecture course in Sapienza University, CS Bachelor's Degree 💾

cpu algorithms storage mips processor assembly asm assembler parallelism mips-assembly assembly-language assembly-language-programming mips-architecture mips-processor assembly-x86 assemblyscript recursive-algorithms asm-mars computer-hardware

Updated Nov 10, 2024
Assembly

yasnakateb / PipelinedMIPS

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🔮 A 16-bit MIPS Processor Implementation in Verilog HDL

cpu pipeline mips verilog icarus-verilog verilog-hdl iverilog mips-processor mips-pipeline

Updated Aug 30, 2020
Verilog

prantoamt / 16bit_processor_design

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processor-architecture cpu mips simulation processor cse mips-assembly hardware-designs computer-architecture mips-assembler logisim mips-language mips-architecture mips-processor mips-simulator computer-design-and-implementation cse332

Updated Dec 30, 2018

jasonlovescoding / MIPS32CPU-5stage-pipelined

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A 5-stage pipelined mips32 processor

verilog course-project mips-processor buaa

Updated May 9, 2017
Verilog

hakula139 / MIPS-CPU

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A MIPS processor with Cache and Advanced Branch Predictor written in SystemVerilog

pipeline cache systemverilog mips-processor branch-prediction

Updated Dec 26, 2020
SystemVerilog

LIU42 / Processor

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《计算机组成原理》课程设计，基于 MIPS 的流水线 CPU 系统设计。

cpu fpga pipeline mips architecture verilog course-project computer-architecture mips-architecture mips-processor homework-project

Updated Aug 27, 2025
Verilog

JosiahMendes / MIPS32-T501

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A low power, high performance 32-bit, 5-cycle MIPS core that implements a subset of instructions.

verilog systemverilog mips-assembler mips-processor mips32

Updated Jun 21, 2021
Verilog

yasnakateb / MIPSProcessor

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🔮 A 32-bit MIPS Processor Implementation in Verilog HDL

cpu xilinx mips-processor multicycle

Updated May 18, 2022
Verilog

mongrelgem / cMIPS

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A complete classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cache.

processor hardware-designs verilog-hdl mips-architecture mips-processor vhdl-code

Updated Sep 3, 2019
Verilog

pariyajebreili / PipelinedMipsProcessor

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A pipelined MIPS processor implemented in Verilog, featuring hazard detection and forwarding.

pipeline verilog computer-architecture hazard-detection mips-processor forwarding-unit

Updated Sep 13, 2025
Verilog

holden-davis-uca / MARS-UCA

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Modification of the MARS program originally written by Kenneth Vollmar and Pete Sanderson at Missouri State University.

java mips mips-assembly mips-assembler mips32cpu mips-language mips-architecture mips-processor mips32 mips-instructions mips-simulator

Updated Feb 10, 2023
HTML

flozzone / DDCA

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Solution for the assignment in Digital Design and Computer Architecture course including test benches running faster than official nightly tests.

vhdl mips-processor

Updated May 19, 2022
VHDL

akankshac-073 / MIPS-5-stage-pipelined-control-and-datapath

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Implementation of a 32-bit 5 stage Pipelined MIPS Processor using RTL coding in Verilog on ModelSim simulator. The processor datapath and control units are designed for Arithmetic and Logical instructions (all r-type instructions + addi, andi, ori, slti), Data transfer instructions (lw, sw), Branch and jump instructions (beq, j). Forwarding cont…

verilog computer-architecture mips-architecture mips-processor mips32 pipelined-processors mips-pipline-processor-verilog