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processor-design

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katef / eurorack-cpu

Sponsor
Star 316

A CPU implemented in a modular synthesizer

modular synthesizer cpu-emulator processor-design
  • Updated Mar 20, 2022

tscheipel / HaDes-V

Star 185

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.

processor-architecture pipelines riscv vivado systemverilog computer-architecture gtkwave system-verilog university-course risc-v c-programming rv32i open-education verilator open-educational-resources processor-design assembly-programming hardware-software-codesign microcontroller-design
  • Updated Feb 2, 2026
  • SystemVerilog

zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial

Star 160

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the fun…

cpu processor simd verilog alu adder instruction-set-architecture cadence-virtuoso multiplier verilog-project processor-design
  • Updated Jul 17, 2022
  • Verilog

peilin-chen / Zhulong-RISCV-CPU

Star 148

CPU Design Based on RISCV ISA

integrated-circuits processor-design
  • Updated Jun 14, 2024
  • Verilog

RISC-KC / basic_rv32s

Star 108

🎓 Instructional RISC-V processor design framework: single-cycle to 5-stage pipeline with FPGA verification and complete learning guidelines! A RISC-V CPU design guideline.

computer-science cpu fpga processor riscv verilog computer-architecture hdl soc verilog-hdl risc-v soft-core rv32i system-on-chip riscv32 dhrystone rv32 processor-design basic-rv32s risc-v-learn
  • Updated Feb 2, 2026
  • Verilog

shehanmunasinghe / tinyGPU

Star 68

tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog

gpu simd systemverilog hdl computer-organization processor-design
  • Updated Jul 14, 2021
  • SystemVerilog

mpskex / chisel-npu

Star 36

Chisel implementation of Neural Processing Unit for System on the Chip

chisel3 system-on-chip processor-design npu
  • Updated Aug 21, 2026
  • C

aofarmakis / Nibbling-bits

Star 35

Design and documentation for a very simple 4-bit processor named NibbleBuddy and its assembler.

assembly assembler verilog computer-architecture instruction-set-architecture computer-organization hardware-description-language processor-design single-cycle-processor
  • Updated Dec 7, 2024
  • Verilog

alirezakay / RISC-CPU

Star 30

A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )

processor-architecture cpu vhdl isa cpu-model instruction-set-architecture mips-processor vhdl-modules risc-processor vhdl-code cpu-architecture multi-cycle processor-design
  • Updated Jun 19, 2021
  • VHDL

Amey-Thakur / COMPUTER-ORGANIZATION-AND-ARCHITECTURE-AND-PROCESSOR-ARCHITECTURE-LAB

Sponsor
Star 23

CSC403: Computer Organization and Architecture [COA] & CSL403: Processor Architecture Lab [PAL] | SE Semester IV | Computer Engineering

computer-science processor-architecture engineering computer-engineering computer-architecture textbooks logisim microprogramming computer-organization booths-algorithm processor-design university-of-mumbai cache-mapping ameythakur amey megasatish reference-books ameyarc amey-thakur processor-architecture-lab
  • Updated Sep 5, 2026
  • HTML

darklife / udarkrisc

Star 20

u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV

cpu fpga core processor rtl verilog risc softcore processor-design
  • Updated Jul 25, 2023
  • Verilog

Awais-Asghar / Single-Cycle-RISC-V-Processor-Implemented-on-FPGA

Star 20

Single-Cycle RISC-V Processor using SystemVerilog on a Nexys A7 (Artix-7) FPGA. Project includes complete datapath and control logic with instruction memory, data memory, ALU, immediate generator, and branch comparator. It supports the complete RV32I instruction set (R, I, S, B, U, J types).

fpga vivado computer-architecture system-verilog risc-v cpu-architecture processor-design single-cycle-processor digital-design-and-computer-organization rv32i-processor
  • Updated Jul 21, 2025
  • SystemVerilog

KevinWang96 / Chip-Multi-processor-System-based-on-Cardinal-Bidirectional-Ring-Network-on-chip

Star 19

EE577b-Course-Project

verilog-hdl multiprocessor processor-design networkonchip synopsys-dc cadence-ncverilog cadence-conformal
  • Updated May 6, 2020
  • Verilog

qossayrida / PipelineProcessorDesign

Star 16

Design and verification of a simple pipelined RISC processor in Verilog, featuring a five-stage pipeline and custom ISA.

verilog pipelining computer-architecture risc processor-design
  • Updated Jul 15, 2024
  • Verilog

AnkurRyder / 8085-Processor

Star 14

8-bit RISC Processor on Logisim

circuit-simulator logisim processor-design
  • Updated Oct 1, 2020

sixblade325 / WaterHand-Processor-Development-Skills

Star 14

Codex skills for Chisel/RISC-V processor development: microarchitecture, RTL verification, Vivado timing analysis, and FPGA optimization.

fpga chisel rtl chisel3 vivado risc-v processor-design cpu-designs loongarch agent-skills codex-cli codex-skills
  • Updated Sep 6, 2026
  • Python

HafizMutahirAhmed / RV32I-5-Stage-Processor

Star 11

A fully pipelined 5-stage RV32I processor implemented in SystemVerilog. This design models instruction-level parallelism with forwarding and hazard detection, and passes all RISCOF compliance tests for the RV32I base ISA.

processor-architecture fpga processor riscv rtl vivado systemverilog hdl risc-v rv32i verilator processor-design fpga-programming arty-a7 risc-v-architecture five-stage riscof pipelined-processor rv32i-processor
  • Updated Jul 27, 2025
  • SystemVerilog

Zaneham / voyager-fds

Sponsor
Star 11

The Voyager flight computer on SKY130 silicon. 58 cells. Currently 24 billion km away.

processor-architecture astronomy nasa space history open-hardware voyager systemverilog hardware-designs new-zealand jpl flight-computer retro-computing processor-design asic-design chip-design skywater-sky130
  • Updated Aug 11, 2026
  • Verilog

Sarst04 / SARV

Star 10

SARV A Risc-V

processor-architecture cpu pipeline core processor verilog computer-architecture risc-v processor-design sarv digital-design-and-computer-architecture
  • Updated Sep 16, 2026
  • Verilog

rj45 / nanogo

Sponsor
Star 9

NanoGo a Go (golang) Subset for Homebrew / Hobby CPUs

go golang cpu compiler assembly hobby-project hobby-compiler processor-design hobby-language homebrew-computer
  • Updated Nov 8, 2025
  • Go

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