Advanced Architecture Labs with CVA6

LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peripherals.

LiteX CVA6 - Fixed integration of the CPU into LiteX SoC generator

Garuda: CVXIF coprocessor optimizing batch-1 attention microkernels with 7.5-9× lower p99 latency. RISC-V INT8 MAC accelerator for transformer inference.

Provides baremetal support for the CVA6 COREV APU on GENESYS2

Yocto layer for OpenHWGroup

These scripts are used in a Vivado project, to implement jtag to axi transactions.

Our work as students (Team Breizh Hat) for the national CVA6 softcore hackathon organized by Thales Group

Investigation of RVA23 profile compliance in the CVA6 (Ariane) RISC-V core, including RTL analysis, extension support evaluation, and potential implementation paths for missing ISA extensions.

This repository contains performance measurement results for a RISC-V CVA6 core running on a PYNQ-Z2 FPGA.

Implementation of TAGE and GShare branch predictors for the CVA6 (Ariane) open-source RISC-V core.

Runs the CVA6 RISC-V core as a real gem5 BaseCPU via the axiom framework. Verilator-simulated RTL bridged to gem5's memory system over a pin-level AXI4 interface. Includes CVA6RTLCpu, a SystemVerilog top-level wrapper, and two passing bare-metal test programs.

Browser-based, cycle-by-cycle pipeline visualizer for the CORE-V CVA6 RISC-V core, reconstructed from Verilator VCD signals.

Examples showing how to connect Tenstorrent rv_tester as a lockstep verification testbench with open-source RISC-V cores (currently CVA6)

Frozen CVA6 fork for the FaMAF CVA6 Project, bundling the MinorFlow and CVA6Flow visualizers.